From 4b1b27e0c1d4f49702fd217fba5d8a87ce59e065 Mon Sep 17 00:00:00 2001
From: Keith Thorne <keith.thorne@ligo.org>
Date: Wed, 5 Jun 2019 13:58:13 -0500
Subject: [PATCH] RB,KT-Changes from trunk4.0 for Debian 9 build

---
 config/Makefile.linux               |  2 +-
 src/epics/util/feCodeGen.pl         |  2 +-
 src/include/drv/iop_adc_functions.c | 14 +++++++-------
 src/include/fe.h                    |  2 +-
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/config/Makefile.linux b/config/Makefile.linux
index 8d154cd30..29e86f985 100644
--- a/config/Makefile.linux
+++ b/config/Makefile.linux
@@ -45,7 +45,7 @@ ifeq (rtlepics,$(findstring rtlepics, $(TARGET)))
 CFLAGS += -DNO_RFM_EPICS_RECORD_SUPPORT
 endif
 CFLAGS += -D_POSIX_C_SOURCE=199506L -D_POSIX_THREADS  
-CFLAGS += -DOSITHREAD_USE_DEFAULT_STACK  -D_X86_  -DUNIX  -D_BSD_SOURCE -Dlinux
+CFLAGS += -DOSITHREAD_USE_DEFAULT_STACK  -D_X86_  -DUNIX  -D_DEFAULT_SOURCE -Dlinux
 CFLAGS += -D_REENTRANT -g -fPIC 
 
 rtl_module := $(shell /sbin/lsmod | grep rtl)
diff --git a/src/epics/util/feCodeGen.pl b/src/epics/util/feCodeGen.pl
index 9da08a2fb..5f0fe678a 100755
--- a/src/epics/util/feCodeGen.pl
+++ b/src/epics/util/feCodeGen.pl
@@ -2676,7 +2676,7 @@ print OUTM "\n";
 
 print OUTM "EXTRA_CFLAGS += -DMODULE -DNO_RTL=1\n";
 print OUTM "EXTRA_CFLAGS += -I\$(SUBDIRS)/../../include -I$rcg_src_dir/src/include\n";
-print OUTM "EXTRA_CFLAGS += -ffast-math -msse2 -mpreferred-stack-boundary=4\n";
+print OUTM "EXTRA_CFLAGS += -ffast-math -m80387 -msse2 -mpreferred-stack-boundary=4\n";
 
 print OUTM "obj-m += $skeleton" . ".o\n";
 
diff --git a/src/include/drv/iop_adc_functions.c b/src/include/drv/iop_adc_functions.c
index 9bf269856..023229ed0 100644
--- a/src/include/drv/iop_adc_functions.c
+++ b/src/include/drv/iop_adc_functions.c
@@ -99,7 +99,7 @@ inline int sync_adc_2_1pps() {
 	    adcDummyData = (int *)cdsPciModules.pci_adc[0];
             adcDummyData += 31;
             gsc16ai64Enable1PPS(jj);
-            // rdtscl(cpuClock[jj]);
+            // rdtscll(cpuClock[jj]);
             status = gsc16ai64WaitDmaDone(0, adcDummyData);
             kk ++;
             udelay(2);
@@ -143,11 +143,11 @@ inline int iop_adc_read (adcInfo_t *adcinfo,int cpuClk[])
         packedData = (int *)cdsPciModules.pci_adc[jj];
         packedData += 31;
 		
-        rdtscl(cpuClk[CPU_TIME_RDY_ADC]);
+        rdtscll(cpuClk[CPU_TIME_RDY_ADC]);
         do {
             /// - ---- Need to delay if not ready as constant banging of the input register
             /// will slow down the ADC DMA.
-            rdtscl(cpuClk[CPU_TIME_ADC_WAIT]);
+            rdtscll(cpuClk[CPU_TIME_ADC_WAIT]);
             adcinfo->adcWait = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_RDY_ADC])/CPURATE;
             /// - ---- Allow 1sec for data to be ready (should never take that long).
         }while((*packedData == DUMMY_ADC_VAL) && (adcinfo->adcWait < MAX_ADC_WAIT));
@@ -191,7 +191,7 @@ inline int iop_adc_read (adcInfo_t *adcinfo,int cpuClk[])
         if(jj == 0) 
         {
         // Capture cpu clock for cpu meter diagnostics
-            rdtscl(cpuClk[CPU_TIME_CYCLE_START]);
+            rdtscll(cpuClk[CPU_TIME_CYCLE_START]);
             /// \> If first cycle of a new second, capture IRIG-B time. Standard for aLIGO is
             /// TSYNC_RCVR.
             if(cycleNum == 0) 
@@ -310,11 +310,11 @@ inline int iop_adc_read_32 (adcInfo_t *adcinfo,int cpuClk[])
         packedData = (int *)cdsPciModules.pci_adc[jj];
         packedData += 63;
 		
-        rdtscl(cpuClk[CPU_TIME_RDY_ADC]);
+        rdtscll(cpuClk[CPU_TIME_RDY_ADC]);
         do {
             /// - ---- Need to delay if not ready as constant banging of the input register
             /// will slow down the ADC DMA.
-            rdtscl(cpuClk[CPU_TIME_ADC_WAIT]);
+            rdtscll(cpuClk[CPU_TIME_ADC_WAIT]);
             adcinfo->adcWait = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_RDY_ADC])/CPURATE;
             /// - ---- Allow 1sec for data to be ready (should never take that long).
         }while((*packedData == DUMMY_ADC_VAL) && (adcinfo->adcWait < MAX_ADC_WAIT));
@@ -352,7 +352,7 @@ inline int iop_adc_read_32 (adcInfo_t *adcinfo,int cpuClk[])
         if(jj == 0) 
         {
         // Capture cpu clock for cpu meter diagnostics
-            rdtscl(cpuClk[CPU_TIME_CYCLE_START]);
+            rdtscll(cpuClk[CPU_TIME_CYCLE_START]);
             /// \> If first cycle of a new second, capture IRIG-B time. Standard for aLIGO is
             /// TSYNC_RCVR.
             if(cycleNum == 0) 
diff --git a/src/include/fe.h b/src/include/fe.h
index 9733aef26..178b77699 100644
--- a/src/include/fe.h
+++ b/src/include/fe.h
@@ -1,7 +1,7 @@
 #include "linux/types.h"
 #include "linux/kernel.h"
 #include "asm/delay.h"
-#include </usr/src/linux/arch/x86/include/asm/processor.h>
+#include "asm/processor.h"
 //extern int printf(const char *, ...) __attribute__((format(printf, 1, 2)));
 //extern int printf(const char *, ...);
 #define printf printk
-- 
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