diff --git a/src/epics/util/feCodeGen.pl b/src/epics/util/feCodeGen.pl
index 4a81c27410a199cd7a0a3fba8968586553dd4a85..556377283e438116f3ca70db2fe5f56352576472 100755
--- a/src/epics/util/feCodeGen.pl
+++ b/src/epics/util/feCodeGen.pl
@@ -1835,7 +1835,6 @@ print "\tPart number is $remoteGpsPart\n";
if($virtualiop == 1) {
print OUT "#include \"$rcg_src_dir/src/fe/controllerVirtual.c\"\n";
} elsif ($virtualiop == 2) {
- print OUTM "EXTRA_CFLAGS += -DTIME_SLAVE=1\n";
print OUT "#include \"$rcg_src_dir/src/fe/controllerIop.c\"\n";
} elsif ($virtualiop == 3) {
print OUT "#include \"$rcg_src_dir/src/fe/controllerLR.c\"\n";
@@ -2629,7 +2628,7 @@ if ($timeMaster > -1) {
print OUTM "#Uncomment to build a time master\n";
print OUTM "#EXTRA_CFLAGS += -DTIME_MASTER=1\n";
}
-if ($timeSlave > -1) {
+if ($timeSlave > -1 or $virtualiop == 2) {
print OUTM "EXTRA_CFLAGS += -DTIME_SLAVE=1\n";
} else {
print OUTM "#Uncomment to build a time slave\n";
diff --git a/src/epics/util/lib/medmGenGdsTp.pm b/src/epics/util/lib/medmGenGdsTp.pm
index 27440ae855b2b4cb581675098146d04a17f604dd..277f3143d27b8e496334010f21338f061e31324b 100644
--- a/src/epics/util/lib/medmGenGdsTp.pm
+++ b/src/epics/util/lib/medmGenGdsTp.pm
@@ -267,7 +267,7 @@ sub createGdsMedm
$medmdata .= ("CDS::medmGen::medmGenTextMon") -> ($xpos,$ypos,$width,$height,"$site\:FEC-$dcuid\_BUILD_DATE",$ecolors{white},$ecolors{blue},"static");
# Following only for IOP
- if($adcMaster == 1 and $ioptype != 4)
+ if($adcMaster == 1 and $ioptype != 4 and $ioptype != 2)
{
# Add ADC Duotone Diag label
$xpos = 18; $ypos = 240; $width = 50; $height = 15;
diff --git a/src/fe/controllerApp.c b/src/fe/controllerApp.c
index 650905cca28cec9dcc091e9c8fd30a83616b2da8..5046e0701571393b440b37ffb2bde99a236adec6 100644
--- a/src/fe/controllerApp.c
+++ b/src/fe/controllerApp.c
@@ -358,6 +358,7 @@ udelay(1000);
}
+
// After first synced ADC read, must set code to read number samples/cycle
sampleCount = OVERSAMPLE_TIMES;
@@ -388,6 +389,13 @@ udelay(1000);
pLocalEpics->epicsOutput.cycle = cycleNum;
+#ifdef NO_CPU_SHUTDOWN
+ if((cycleNum % 2048) == 0) {
+ usleep_range(1,3);
+ printk("cycleNum = %d\n",cycleNum);
+ }
+#endif
+
// **********************************************************************
/// \> Cycle 18, Send timing info to EPICS at 1Hz
// **********************************************************************
diff --git a/src/fe/controllerIop.c b/src/fe/controllerIop.c
index 4397b03064473e316c294dcac93af6b569739c9c..938eb36420cf278a98d5b01f2e52f7ba401f49ff 100644
--- a/src/fe/controllerIop.c
+++ b/src/fe/controllerIop.c
@@ -182,9 +182,13 @@ adcInfo_t *padcinfo = (adcInfo_t *)&adcinfo;
#endif
-#ifdef TIME_MASTER
+#ifdef TIME_MASTER
pcieTimer = (TIMING_SIGNAL *) ((volatile char *)(cdsPciModules.dolphinWrite[0]) + IPC_PCIE_TIME_OFFSET);
#endif
+#ifdef TIME_SLAVE
+ pcieTimer = (TIMING_SIGNAL *) ((volatile char *)(cdsPciModules.dolphinRead[0]) + IPC_PCIE_TIME_OFFSET);
+syncSource = SYNC_SRC_DOLPHIN;
+#endif
/// < Read in all Filter Module EPICS coeff settings
for(ii=0;ii<MAX_MODULES;ii++)
@@ -289,10 +293,6 @@ adcInfo_t *padcinfo = (adcInfo_t *)&adcinfo;
pLocalEpics->epicsOutput.fe_status = INIT_SYNC;
-#ifdef TIME_SLAVE
-syncSource = SYNC_SRC_DOLPHIN;
-#else
-
/// \> Find the code syncrhonization source. \n
/// - Standard aLIGO Sync source is the Timing Distribution System (TDS) (SYNC_SRC_TDS).
switch(syncSource)
@@ -367,7 +367,6 @@ syncSource = SYNC_SRC_DOLPHIN;
break;
}
}
-#endif
// for(jj=0;jj<cdsPciModules.adcCount;jj++) gsc18ai32DmaEnable(jj);
pLocalEpics->epicsOutput.fe_status = NORMAL_RUN;
@@ -423,9 +422,7 @@ syncSource = SYNC_SRC_DOLPHIN;
if(!iopDacEnable || dkiTrip) feStatus |= FE_ERROR_DAC_ENABLE;
/// - ---- If IOP, Increment GPS second
-#ifndef TIME_SLAVE
timeSec ++;
-#endif
pLocalEpics->epicsOutput.timeDiag = timeSec;
if (cycle_gps_time == 0) {
timeinfo.startGpsTime = timeSec;
@@ -434,9 +431,8 @@ syncSource = SYNC_SRC_DOLPHIN;
cycle_gps_time = timeSec;
}
#ifdef NO_CPU_SHUTDOWN
- if((cycleNum % 65536) == 0) {
+ if((cycleNum % 2048) == 0) {
usleep_range(1,3);
- printk("cycleNum = %d\n",cycleNum);
}
#endif
// Start of ADC Read **********************************************************************
@@ -557,15 +553,18 @@ for(usloop=0;usloop<UNDERSAMPLE;usloop++)
}
/// \> Update duotone diag information
+ if(syncSource == SYNC_SRC_TDS)
+ {
dt_diag.dac[(cycleNum + DT_SAMPLE_OFFSET) % CYCLE_PER_SECOND] = dWord[ADC_DUOTONE_BRD][DAC_DUOTONE_CHAN][usloop];
dt_diag.totalDac += dWord[ADC_DUOTONE_BRD][DAC_DUOTONE_CHAN][usloop];
dt_diag.adc[(cycleNum + DT_SAMPLE_OFFSET) % CYCLE_PER_SECOND] = dWord[ADC_DUOTONE_BRD][ADC_DUOTONE_CHAN][usloop];
dt_diag.totalAdc += dWord[ADC_DUOTONE_BRD][ADC_DUOTONE_CHAN][usloop];
+ }
// *****************************************************************
/// \> Cycle 16, perform duotone diag calcs.
// *****************************************************************
- if(cycleNum == HKP_DT_CALC)
+ if(cycleNum == HKP_DT_CALC && syncSource == SYNC_SRC_TDS)
{
duotoneTime = duotime(DT_SAMPLE_CNT, dt_diag.meanAdc, dt_diag.adc);
pLocalEpics->epicsOutput.dtTime = duotoneTime;
@@ -579,7 +578,7 @@ for(usloop=0;usloop<UNDERSAMPLE;usloop++)
// *****************************************************************
/// \> Cycle 17, set/reset DAC duotone switch if request has changed.
// *****************************************************************
- if(cycleNum == HKP_DAC_DT_SWITCH)
+ if(cycleNum == HKP_DAC_DT_SWITCH && syncSource == SYNC_SRC_TDS)
{
if(dt_diag.dacDuoEnable != pLocalEpics->epicsInput.dacDuoSet)
{
@@ -843,6 +842,7 @@ for(usloop=0;usloop<UNDERSAMPLE;usloop++)
// Check once per second on code cycle HKP_DAC_WD_CHK to dac count
// Only one read per code cycle to reduce time
// *****************************************************************
+#ifndef TIME_SLAVE
if (cycleNum >= HKP_DAC_WD_CHK && cycleNum < (HKP_DAC_WD_CHK + cdsPciModules.dacCount))
{
jj = cycleNum - HKP_DAC_WD_CHK;
@@ -869,6 +869,7 @@ for(usloop=0;usloop<UNDERSAMPLE;usloop++)
pLocalEpics->epicsOutput.statDac[jj] |= DAC_WD_BIT;
}
}
+#endif
// *****************************************************************
/// \> Cycle 600 to 600 + numDacModules, Check DAC FIFO Sizes to determine if DAC modules are synched to code
diff --git a/src/include/drv/time_slave_io.c b/src/include/drv/time_slave_io.c
index ef2017178599682358883c5258f3c8817947c72e..42a160d83f46fe66744dea040ec8e0c5db60e392 100644
--- a/src/include/drv/time_slave_io.c
+++ b/src/include/drv/time_slave_io.c
@@ -25,9 +25,11 @@ sync2master( TIMING_SIGNAL* timePtr )
loop++;
} while ( timePtr->cycle != cycle && loop < 1000000 );
if ( loop >= 1000000 )
+ {
return ( -1 );
- else
+ } else {
return ( timePtr->gps_time );
+ }
}
inline int