Fix feCodeGen.pl for timing slaves

See TST log 12993. The feCodeGen.pl needs to be corrected to handle timing slaves without IO chassis

A suggested fix controls@x2boot2:/opt/rtcds/rtscore/advligorts$ git diff src/epics/util/feCodeGen.pl diff --git a/src/epics/util/feCodeGen.pl b/src/epics/util/feCodeGen.pl index c2c630e5..1ec6755a 100755 --- a/src/epics/util/feCodeGen.pl +++ b/src/epics/util/feCodeGen.pl @@ -1492,10 +1492,10 @@ for(ii=0;ii<partCnt;ii++) print OUTH "#define TARGET_DAC18_COUNT $dac18Cnt\n"; print OUTH "#define TARGET_DAC20_COUNT $dac20Cnt\n"; } else {

```
          if($virtualiop) {
```

                  print OUTH "\#define TARGET_ADC_COUNT 0\n";

```
          } else {
```

          if($virtualiop == 0 and $adcMaster == 1) {
                  print OUTH "\#define TARGET_ADC_COUNT 1\n";

```
          } else {
```

                  print OUTH "\#define TARGET_ADC_COUNT 0\n";
          }
          print OUTH "\#define TARGET_DAC16_COUNT 0\n";
          print OUTH "\#define TARGET_DAC18_COUNT 0\n";