Enable setting of high-speed ADCs to different clock speeds
In the present RCG, if you set things to allow for high-rate ADC clocks in the IOP model (i.e. rate=512K, clock_div=8), it runs the old 16-bit ADCs at 64 KHz and any high-rate capable ADC at 512 KHz
If we have both a 'Fast ADC' (18 bit but up to 1 MHz) and a 'low-noise' ADC (18-bit up to 750 kHz), it runs both at 512 KHz. The extra processing of 8 samples from each of these is too much for at 64 KHz real-time loop with current hardware.
We at least need the ability to run them at either the fast rate (here 512 KHz) or the clock-divided rate (64 KHz) used for the older ADCs.