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Update cdsParameters authored by Ezekiel Dohmen's avatar Ezekiel Dohmen
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cdsParameters.md
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- IOP models must define to be built as and [IOP model](https://git.ligo.org/cds/software/advligorts/-/wikis/Model-Class-Types#input-output-processor-iop-models) by the RCG.
- One model per front end will be an IOP model.
# Other Common Fields
## IOP Only
- `dolphin_time_xmit=1`
- Causes this model to write the transmit the time over the dolphin network.
- Only ONE transmitter should be configured on a dolphin network.
......@@ -49,74 +53,87 @@ This page documents each parameter and its use, for documentation on common sets
- Causes the model to read the time from the dolphin network.
- Useful for systems with no timing hardware, but with a dolphin connection.
- `pciRfm=1`
- Causes the model to attempt to initialize with the dolphin network
- Must be set to use PCIE/RFM IPC or for timing functions over dolphin
- `rfm_delay=<VAL>`
- VAL: is a number of cycles at the models rate that the model should write ahead in the IPC buffers.
- This is used to compensate for long delays in RFM IPCs over long distances
- `requireIOcnt= `
- Causes the model to attempt to initialize with the dolphin network.
- Must be set to use PCIE/RFM IPC or for timing functions over dolphin.
- `requireIOcnt=<VAL>`
- Options
- `0` Don't require all configured IO (ADC/DAC) to be present when running
- `1` Exit if the configured IO is different than expected
- `vectorization=<VAL>`
- Valid Options
- `avx2`
- `sse3`
- Enables vectorization extensions in the compiler
- `0` Don't require all configured IO (ADC/DAC) to be present when running.
- `1` Exit if the configured IO is different than expected. (This is the default)
- `clock_div=<val>`
- This is the number of samples to process during a cycle at the model rate.
- The fast-IOP, `rate=512K` uses a `clock_div=8`. 524288/8 = 65536 so user models get filtered/decimated data at the default expected IOP rate.
- `optimizeIO=1`
- When set, the IOP will not preload the DAC FIFOs with the usual 2 samples at startup. This can provide for lower phase delay for 2 clock cycles, or 30 usec at the typical 64K IOP rate.
- `time0_delay_us=<VAL>`
- This value is subtracted off the time 0 calculation for IOP models.
- This is useful for models that run on front ends with an IO chassis .
## IOP and Control Models
- `ipc_rate=<VAL>`
- This can be used to lower the IPC rate of models below their model rate.
- The `ipc_rate` must be less than or equal to the model rate.
- For model rates faster than 65536, the `ipc_rate` must be passed in as a parameter (set to <= 65536).
- `time0_delay_us=<VAL>`
- This value is subtracted off the time 0 calculation for IOP models.
- This is useful for models that run on front ends with an IO chassis
- `vectorization=<VAL>`
- Valid Options
- `avx2`
- `sse3`
- Enables vectorization extensions in the compiler for this model.
- `rfm_delay=<VAL>`
- VAL: is a number of cycles at the models rate that the model should write ahead in the IPC buffers.
- This is used to compensate for long delays in RFM IPCs over long distances .
# Other Fields
These options are supported, but don't get a lot of use.
## IOP Only
- `no_sync=1`
- Disables the check for a 1 PPS signal (TIME 0)
- Useful for systems with a 65536Hz TTL and no PPS (Often a CyMAC configuration)
- `no_daq=1`
- Build the model without the ability to write DAQ data to shared memory.
- `test1pps=1`
- Used to build the model for testing purposes.
- `diagTest=1`
- Builds the model with special testing code and functions
- Used in the ATS automated testing system
- `daq_prefix=<VAR>`
- TODO
- `remoteGPS=``
- TODO
- `no_cpu_shutdown=1`
- Causes the model to skip any core isolation procedures
- `flip_signals=1`
- Causes all ADC and DAC data to be multiplied by -1 when being read and before being written by the IOP.
- `sdf=1`
- `virtualIOP=1`
- Enables logic so you can run an IOP model on a system without any ADCs/DACs
- `bio_test=1`
- Adds a test where we read back what we write to the BIO modules
- `internalclk=1`
- Configures the ADC to used an internally generated 64K clock
- `no_zero_pad=1`
- Causes the DAC output to not be zero padded for filtering. Instead the DAC output value is repeatedly run thru the filter `clock_div` time.
## IOP and Control Models
- `no_daq=1`
- Build the model without the ability to write DAQ data to shared memory.
- `no_cpu_shutdown=1`
- Causes the model to skip any core isolation procedures
- `daq_prefix=<VAR>`
- TODO
- `casdf=1`
- `remoteGPS=`
- TODO
- `noiseGeneratorSeed=<VAL>`
- Sets an integer seed for all noise generated by uniform noise parts.
- `gaussNoiseGeneratorSeed=<VAL>`
- Sets an integer seed for all noise generated by Gaussian noise parts.
- `virtualIOP=1`
- Enables logic so you can run an IOP model on a system without any ADCs/DACs
- `use_shm_ipc=1`
- Regardless of IPC type definition in the Matlab model, the RCG will force all IPCs to be defined as SHMEM type.
- This can be useful in running a production system model, most of which use PCIe type IPC, in a standalone system for testing.
- `adcclock=128`
- Used in IOP models with a `rate=128Hz`, to pass data at 131072 Hz
- Most user models, of various rates, will automatically handle data from their IOP model. However when IOP's are configured to pass data faster than 64K, this parameter will be needed.
- `bio_test=1`
- Adds a test where we read back what we write to the BIO modules
- `internalclk=1`
- Configures the ADC to used an internally generated 64K clock
- `no_zero_pad=1`
- Causes the DAC output to not be zero padded for filtering. Instead the DAC output value is repeatedly run thru the filter `clock_div` time.
## Control Models Only
- `sdf=1`
- TODO
- `casdf=1`
- TODO
### Userspace Only
- `userspacegps=1`
- TODO
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