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- The fast-IOP, `rate=512K` uses a `clock_div=8`. 524288/8 = 65536 so user models get filtered/decimated data at the default expected IOP rate.
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- `optimizeIO=1`
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- When set, the IOP will not preload the DAC FIFOs with the usual 2 samples at startup. This can provide for lower phase delay for 2 clock cycles, or 30 usec at the typical 64K IOP rate.
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- Open issue with this parameter if issue #649 is still open.
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- `time0_delay_us=<VAL>`
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- This value is subtracted off the time 0 calculation for IOP models.
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- This is useful for models that run on front ends with an IO chassis .
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