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-This line, and those below, will be ignored--

M    Makefile


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writing new values to the output buffer while DAC is in process of DMA data out.


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Bug Fix. Bit2Word.pm would define powers_of_2 multiple times when model contains multiple parts of this type, which all
use the same variable.


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farther out (by a factor of 10) to allow more room for the DCU IPC
areas now that we have more than a 100 DCUs.
Room for up to 399 DCUs provided now.


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Switched EzCaRead to use sequencer pvPuts rather than ezca call.
Parser3 code fix for the removal of busses (source port was not assigned).


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were broken in some cases



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'-c' was added in order to generate sequencer code that will not try to
connect all channels, but will start running even though there are disconencted channels.
This is needed for the models using EzCa parts.


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This is important to allow one-to-many tags.


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New Features:
1) RCG provides default code rate in coeff.txt files for use by foton.
2) New IIR filter part based on BiQuad filter algorithm as provided by M. Evans.
3) Ability to include a user-defined library part in an RCG model.
4) Support for connection of buses between multiple layers of the model, not just on save level.
5) Auto-generated EPICS.ini files for each model.
6) Check of 16bit DAC module FIFOs for proper clocking plus new error bit added to GDS_TP screens..
7) Change of _DAQ to _DQ tag on filter modules in DAQ .ini files.

Bug Fixes:
1) Fix to EPICS EZCA part to:
	- compile correctly within subsystem parts.
	- Use pvPut instead of EZCA for performance reasons (plus EZCA not supported in latest EPICS).
2) Removal of SVN tag from BURT file ie BURT restore would overwrite latest SVN tag).
3) Fix to slave model DAC status info on GDS TP screens (false error indicator).
4) Change in CDS_PARTS.mdl bus selector part to set use to "Require input signal names to match signals below", instead of "Inheri
		t bus signal names from input ports". This is required to make BUS parts work with new, multi-level BUS parser in RCG.


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With this parameter set the busses can be used to go in and out of nested subsystems.


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1) Fix to ADC/DAC status bits on GDS_TP screens
	- More DAC bits to reflect added DAC FIFO and WD errors
	- Fix to DAC error bit displays on system compiled with adcSlave
		- Got rid of bogous red status bit.
2) In testing, found that RCG did not catch error if input to a top level
subsystem part is not connected. This is fixed, and code will exit with
error message after producing list of non-connections found.


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2) Moved above, plus remove_buses, after the model is flattened ie neither
of the above work until after the flattening process.


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trunk/target/MODEL_EPICS_DIR/db/IFO directory as auto.ini. The install section still
needs to be modified to move it to proper location in chans/daq.

Removed SVN from autoBurt file generation. Previously, BURT saved this setting and
a restore would overwrite the proper SVN number of the running code.


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Moved FIFO not empty error bit to bit 3 in dac status for both 18 and 16 bit DACs.
Moved AI chassis watchdog error bit for 18bit DAC modules to bit 4.


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