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Qi Chu authored
pipe_macro.h, pipemodules/pipe_macro.py: change the lower-limit of chisq bins from 10**-1.2=0.063 to 10**-0.4=0.398 all the background or zerolag events that have chisq < 0.398 will be assigned to the first bin
8f5437cd
pipe_macro.h, pipemodules/pipe_macro.py: change the lower-limit of chisq bins from 10**-1.2=0.063 to 10**-0.4=0.398 all the background or zerolag events that have chisq < 0.398 will be assigned to the first bin