Commit 8f5437cd authored by Qi Chu's avatar Qi Chu

pipe_macro.h, pipemodules/pipe_macro.py: change the lower-limit of chisq bins...

pipe_macro.h, pipemodules/pipe_macro.py: change the lower-limit of chisq bins from 10**-1.2=0.063 to 10**-0.4=0.398
all the background or zerolag events that have chisq < 0.398 will be assigned to the first bin
parent a2f9b410
......@@ -54,7 +54,7 @@ int get_ifo_idx(char *ifo);
#define LOGSNR_CMIN 0.54 // center of the first bin
#define LOGSNR_CMAX 3.0 // center of the last bin
#define LOGSNR_NBIN 300 // step is 0.01
#define LOGCHISQ_CMIN -1.2
#define LOGCHISQ_CMIN -0.4
#define LOGCHISQ_CMAX 3.5
#define LOGCHISQ_NBIN 300
......
......@@ -5,9 +5,9 @@ xmax = 3.0
xstep = 0.0082
xbin = 300
# chisq
ymin = -1.2
ymin = -0.4
ymax = 3.5
ystep = 0.0157
ystep = 0.013
ybin = 300
# rank
......
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