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Commit ab2db469 authored by Rolf Bork's avatar Rolf Bork
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Just some clean up before adding more timing checks. 

git-svn-id: https://redoubt.ligo-wa.caltech.edu/svn/advLigoRTS/trunk@4837 6dcd42c9-f523-4c6d-aada-af552506706e
parent 96d7f3b1
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src/include/drv/iop_adc_functions.c
+ 141
− 153
View file @ ab2db469
......@@ -54,7 +54,7 @@ inline int sync_adc_2_1pps() {
kk = 0;
for(jj=0;jj<cdsPciModules.adcCount;jj++)
{
adcDummyData = (int *)cdsPciModules.pci_adc[0];
adcDummyData = (int *)cdsPciModules.pci_adc[0];
adcDummyData += 31;
gsc16ai64Enable1PPS(jj);
// rdtscl(cpuClock[jj]);
......@@ -81,163 +81,151 @@ inline int sync_adc_2_1pps() {
}
// ADC Read *****************************************************************
inline int iop_adc_read (adcInfo_t *adcinfo,int cpuClk[])
{
int ii,jj;
volatile int *packedData;
int limit;
int mask;
unsigned int offset;
int num_outs;
int ioMemCntr = 0;
// Start of ADC Read *****************************************************************
/// \> IF IOP, Wait for ADC data ready
/// - ---- On startup, only want to read one sample such that first cycle
/// coincides with GPS 1PPS. Thereafter, sampleCount will be
/// increased to appropriate number of 65536 s/sec to match desired
/// code rate eg 32 samples each time thru before proceeding to match 2048 system.
// Read ADC data
for(jj=0;jj<cdsPciModules.adcCount;jj++)
{
/// - ---- ADC DATA RDY is detected when last channel in memory no longer contains the
/// dummy variable written during initialization and reset after the read.
packedData = (int *)cdsPciModules.pci_adc[jj];
if (cdsPciModules.adcType[jj] == GSC_18AISS6C) packedData += 5;
else packedData += 31;
int ii,jj;
volatile int *packedData;
int limit;
int mask;
unsigned int offset;
int num_outs;
int ioMemCntr = 0;
// Read ADC data
for(jj=0;jj<cdsPciModules.adcCount;jj++)
{
/// - ---- ADC DATA RDY is detected when last channel in memory no longer contains the
/// dummy variable written during initialization and reset after the read.
packedData = (int *)cdsPciModules.pci_adc[jj];
packedData += 31;
rdtscl(cpuClk[CPU_TIME_RDY_ADC]);
do {
/// - ---- Need to delay if not ready as constant banging of the input register
/// will slow down the ADC DMA.
// if(*packedData == DUMMY_ADC_VAL) {
rdtscl(cpuClk[CPU_TIME_ADC_WAIT]);
adcinfo->adcWait = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_RDY_ADC])/CPURATE;
// }
/// - ---- Allow 1sec for data to be ready (should never take that long).
}while((*packedData == DUMMY_ADC_VAL) && (adcinfo->adcWait < MAX_ADC_WAIT));
rdtscl(cpuClk[CPU_TIME_RDY_ADC]);
do {
/// - ---- Need to delay if not ready as constant banging of the input register
/// will slow down the ADC DMA.
rdtscl(cpuClk[CPU_TIME_ADC_WAIT]);
adcinfo->adcWait = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_RDY_ADC])/CPURATE;
/// - ---- Allow 1sec for data to be ready (should never take that long).
}while((*packedData == DUMMY_ADC_VAL) && (adcinfo->adcWait < MAX_ADC_WAIT));
/// - ---- Added ADC timing diagnostics to verify timing consistent and all rdy together.
if(jj==0) {
adcinfo->adcRdTime[jj] = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_CYCLE_START]) / CPURATE;
if(jj==0) {
adcinfo->adcRdTime[jj] = (cpuClk[CPU_TIME_ADC_WAIT] - cpuClk[CPU_TIME_CYCLE_START]) / CPURATE;
#ifdef TIME_MASTER
pcieTimer->gps_time = timeSec;
pcieTimer->cycle = cycleNum;
#endif
} else {
adcinfo->adcRdTime[jj] = adcinfo->adcWait;
}
if(adcinfo->adcRdTime[jj] > adcinfo->adcRdTimeMax[jj]) adcinfo->adcRdTimeMax[jj] =
adcinfo->adcRdTime[jj];
if((jj==0) && (adcinfo->adcRdTimeMax[jj] > MAX_ADC_WAIT_CARD_0))
adcinfo->adcRdTimeErr[jj] ++;
if((jj!=0) && (adcinfo->adcRdTimeMax[jj] > MAX_ADC_WAIT_CARD_S))
adcinfo->adcRdTimeErr[jj] ++;
/// - --------- If data not ready in time, abort.
/// Either the clock is missing or code is running too slow and ADC FIFO
/// is overflowing.
if (adcinfo->adcWait >= MAX_ADC_WAIT) {
pLocalEpics->epicsOutput.stateWord = FE_ERROR_ADC;
pLocalEpics->epicsOutput.diagWord |= ADC_TIMEOUT_ERR;
stop_working_threads = 1;
vmeDone = 1;
printf("timeout %d %d \n",jj,adcinfo->adcWait);
continue;
}
if(jj == 0)
{
// Capture cpu clock for cpu meter diagnostics
rdtscl(cpuClk[CPU_TIME_CYCLE_START]);
/// \> If first cycle of a new second, capture IRIG-B time. Standard for aLIGO is
/// TSYNC_RCVR.
if(cycleNum == 0)
{
// if SymCom type, just do write to lock current time and read later
// This save a couple three microseconds here
if(cdsPciModules.gpsType == SYMCOM_RCVR) lockGpsTime();
if(cdsPciModules.gpsType == TSYNC_RCVR)
{
/// - ---- Reading second info will lock the time register, allowing
/// nanoseconds to be read later (on next cycle). Two step process used to
/// save CPU time here, as each read can take 2usec or more.
timeSec = getGpsSecTsync();
}
}
}
/// \> Read adc data
packedData = (int *)cdsPciModules.pci_adc[jj];
/// - ---- First, and only first, channel should have upper bit marker set.
/// If not, have a channel hopping error.
if(!(*packedData & ADC_1ST_CHAN_MARKER))
{
adcinfo->adcChanErr[jj] = 1;
adcinfo->chanHop = 1;
pLocalEpics->epicsOutput.stateWord |= FE_ERROR_ADC;
}
limit = OVERFLOW_LIMIT_16BIT;
if (cdsPciModules.adcType[jj] == GSC_18AISS6C) {
limit = OVERFLOW_LIMIT_18BIT; // 18 bit limit
offset = GSAF_DATA_CODE_OFFSET; // Data coding offset in 18-bit DAC
mask = GSAF_DATA_MASK;
num_outs = GSAF_CHAN_COUNT;
} else {
// Various ADC models have different number of channels/data bits
offset = GSAI_DATA_CODE_OFFSET;
mask = GSAI_DATA_MASK;
num_outs = GSAI_CHAN_COUNT;
}
/// - ---- Determine next ipc memory location to load ADC data
ioMemCntr = (cycleNum % IO_MEMORY_SLOTS);
/// - ---- Read adc data from PCI mapped memory into local variables
for(ii=0;ii<num_outs;ii++)
{
// adcData is the integer representation of the ADC data
adcinfo->adcData[jj][ii] = (*packedData & mask);
adcinfo->adcData[jj][ii] -= offset;
} else {
adcinfo->adcRdTime[jj] = adcinfo->adcWait;
}
if(adcinfo->adcRdTime[jj] > adcinfo->adcRdTimeMax[jj]) adcinfo->adcRdTimeMax[jj] =
adcinfo->adcRdTime[jj];
if((jj==0) && (adcinfo->adcRdTimeMax[jj] > MAX_ADC_WAIT_CARD_0))
adcinfo->adcRdTimeErr[jj] ++;
if((jj!=0) && (adcinfo->adcRdTimeMax[jj] > MAX_ADC_WAIT_CARD_S))
adcinfo->adcRdTimeErr[jj] ++;
/// - --------- If data not ready in time, abort.
/// Either the clock is missing or code is running too slow and ADC FIFO
/// is overflowing.
if (adcinfo->adcWait >= MAX_ADC_WAIT) {
pLocalEpics->epicsOutput.stateWord = FE_ERROR_ADC;
pLocalEpics->epicsOutput.diagWord |= ADC_TIMEOUT_ERR;
stop_working_threads = 1;
vmeDone = 1;
printf("timeout %d %d \n",jj,adcinfo->adcWait);
continue;
}
if(jj == 0)
{
// Capture cpu clock for cpu meter diagnostics
rdtscl(cpuClk[CPU_TIME_CYCLE_START]);
/// \> If first cycle of a new second, capture IRIG-B time. Standard for aLIGO is
/// TSYNC_RCVR.
if(cycleNum == 0)
{
// if SymCom type, just do write to lock current time and read later
// This save a couple three microseconds here
if(cdsPciModules.gpsType == SYMCOM_RCVR) lockGpsTime();
if(cdsPciModules.gpsType == TSYNC_RCVR)
{
/// - ---- Reading second info will lock the time register, allowing
/// nanoseconds to be read later (on next cycle). Two step process used to
/// save CPU time here, as each read can take 2usec or more.
timeSec = getGpsSecTsync();
}
}
}
/// \> Read adc data
packedData = (int *)cdsPciModules.pci_adc[jj];
/// - ---- First, and only first, channel should have upper bit marker set.
/// If not, have a channel hopping error.
if(!(*packedData & ADC_1ST_CHAN_MARKER))
{
adcinfo->adcChanErr[jj] = 1;
adcinfo->chanHop = 1;
pLocalEpics->epicsOutput.stateWord |= FE_ERROR_ADC;
}
limit = OVERFLOW_LIMIT_16BIT;
// Various ADC models have different number of channels/data bits
offset = GSAI_DATA_CODE_OFFSET;
mask = GSAI_DATA_MASK;
num_outs = GSAI_CHAN_COUNT;
/// - ---- Determine next ipc memory location to load ADC data
ioMemCntr = (cycleNum % IO_MEMORY_SLOTS);
/// - ---- Read adc data from PCI mapped memory into local variables
for(ii=0;ii<num_outs;ii++)
{
// adcData is the integer representation of the ADC data
adcinfo->adcData[jj][ii] = (*packedData & mask);
adcinfo->adcData[jj][ii] -= offset;
#ifdef DEC_TEST
if(ii==0)
{
adcinfo->adcData[jj][ii] = dspPtr[0]->data[0].exciteInput;
}
if(ii==0)
{
adcinfo->adcData[jj][ii] = dspPtr[0]->data[0].exciteInput;
}
#endif
// dWord is the double representation of the ADC data
// This is the value used by the rest of the code calculations.
dWord[jj][ii] = adcinfo->adcData[jj][ii];
/// - ---- Load ADC value into ipc memory buffer
ioMemData->iodata[jj][ioMemCntr].data[ii] = adcinfo->adcData[jj][ii];
packedData ++;
}
/// - ---- Write GPS time and cycle count as indicator to slave that adc data is ready
ioMemData->gpsSecond = timeSec;;
ioMemData->iodata[jj][ioMemCntr].timeSec = timeSec;;
ioMemData->iodata[jj][ioMemCntr].cycle = cycleNum;
/// - ---- Check for ADC overflows
for(ii=0;ii<num_outs;ii++)
{
if((adcinfo->adcData[jj][ii] > limit) || (adcinfo->adcData[jj][ii] < -limit))
{
adcinfo->overflowAdc[jj][ii] ++;
pLocalEpics->epicsOutput.overflowAdcAcc[jj][ii] ++;
overflowAcc ++;
adcinfo->adcOF[jj] = 1;
odcStateWord |= ODC_ADC_OVF;
}
}
/// - ---- Clear out last ADC data read for test on next cycle
packedData = (int *)cdsPciModules.pci_adc[jj];
*packedData = 0x0;
if (cdsPciModules.adcType[jj] == GSC_18AISS6C) packedData += GSAF_CHAN_COUNT_M1;
else packedData += GSAI_CHAN_COUNT_M1;
*packedData = DUMMY_ADC_VAL;
// dWord is the double representation of the ADC data
// This is the value used by the rest of the code calculations.
dWord[jj][ii] = adcinfo->adcData[jj][ii];
/// - ---- Load ADC value into ipc memory buffer
ioMemData->iodata[jj][ioMemCntr].data[ii] = adcinfo->adcData[jj][ii];
packedData ++;
}
/// - ---- Write GPS time and cycle count as indicator to slave that adc data is ready
ioMemData->gpsSecond = timeSec;;
ioMemData->iodata[jj][ioMemCntr].timeSec = timeSec;;
ioMemData->iodata[jj][ioMemCntr].cycle = cycleNum;
/// - ---- Check for ADC overflows
for(ii=0;ii<num_outs;ii++)
{
if((adcinfo->adcData[jj][ii] > limit) || (adcinfo->adcData[jj][ii] < -limit))
{
adcinfo->overflowAdc[jj][ii] ++;
pLocalEpics->epicsOutput.overflowAdcAcc[jj][ii] ++;
overflowAcc ++;
adcinfo->adcOF[jj] = 1;
odcStateWord |= ODC_ADC_OVF;
}
}
/// - ---- Clear out last ADC data read for test on next cycle
packedData = (int *)cdsPciModules.pci_adc[jj];
*packedData = 0x0;
if (cdsPciModules.adcType[jj] == GSC_18AISS6C) packedData += GSAF_CHAN_COUNT_M1;
else packedData += GSAI_CHAN_COUNT_M1;
*packedData = DUMMY_ADC_VAL;
#ifdef DIAG_TEST
// For DIAGS ONLY !!!!!!!!
......@@ -245,11 +233,11 @@ inline int iop_adc_read (adcInfo_t *adcinfo,int cpuClk[])
// -- Greater than normal will result in channel hopping.
// -- Less than normal will result in ADC timeout.
// In both cases, real-time kernel code should exit with errors to dmesg
if(pLocalEpics->epicsInput.bumpAdcRd != 0) {
gsc16ai64DmaBump(jj,pLocalEpics->epicsInput.bumpAdcRd);
pLocalEpics->epicsInput.bumpAdcRd = 0;
}
if(pLocalEpics->epicsInput.bumpAdcRd != 0) {
gsc16ai64DmaBump(jj,pLocalEpics->epicsInput.bumpAdcRd);
pLocalEpics->epicsInput.bumpAdcRd = 0;
}
#endif
}
return 0;
}
return 0;
}
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