Updated driver code for PCIe timing card to match changes made to firmware.

src/include/drv/ligoPcieTiming.c

@@ -76,10 +76,12 @@ lptcInit( CDS_HARDWARE* pCds, struct pci_dev* lptcdev )
         case GSC_18AO8:
         case GSC_20AO8:
         default:
+            lptcPtr->slot_info[ ii ].config =
+                ( LPTC_SCR_DAC_SET | IOC_CLK_SLOW );
             break;
         }
-	if(ii > 1)
-            lptcPtr->slot_info[ ii ].config |=  LPTC_SCR_DT_DISABLE ;
+	if(ii == 0)
+            lptcPtr->slot_info[ ii ].config |=  LPTC_SCR_ADC_DT_ENABLE ;
         msleep( 10 );
         regval = lptcPtr->slot_info[ ii ].config;
         printk( "Slot Info %d Config = 0x%x\n", ii, regval );
@@ -155,14 +157,14 @@ void
 lptc_dac_duotone( CDS_HARDWARE* pCds, int setting )
 {
     LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
-    if ( !setting )
+    if ( setting )
     {
-        lptcPtr->slot_info[ 0 ].config |= LPTC_SCR_DT_ENABLE;
-        lptcPtr->slot_info[ 1 ].config |= LPTC_SCR_DT_ENABLE;
+        lptcPtr->slot_info[ 0 ].config |= LPTC_SCR_DAC_DT_ENABLE;
+        lptcPtr->slot_info[ 1 ].config |= LPTC_SCR_DAC_DT_ENABLE;
     }
     else
     {
-        lptcPtr->slot_info[ 0 ].config &= ~( LPTC_SCR_DT_ENABLE );
-        lptcPtr->slot_info[ 1 ].config &= ~( LPTC_SCR_DT_ENABLE );
+        lptcPtr->slot_info[ 0 ].config &= ~( LPTC_SCR_DAC_DT_ENABLE );
+        lptcPtr->slot_info[ 1 ].config &= ~( LPTC_SCR_DAC_DT_ENABLE );
     }
 }

src/include/drv/ligoPcieTiming.h

@@ -40,8 +40,8 @@ typedef struct LPTC_DIAG_INFO {
 #define LPTC_SCR_CLK_ENABLE		0x100
 #define LPTC_SCR_ADC_SET		0x1300
 #define LPTC_SCR_DAC_SET		0x1100
-#define LPTC_SCR_DT_ENABLE		0x40000
-#define LPTC_SCR_DT_DISABLE		0x60000
+#define LPTC_SCR_ADC_DT_ENABLE		0x20000
+#define LPTC_SCR_DAC_DT_ENABLE		0x40000
 
 #define LPTC_STATUS_OK 			0x80000000
 #define LPTC_STATUS_ROOT_NODE 		0x40000000