rcg: Moved sequence check into /src/python dir.  Improved sequence error message.  Fixed some typos and formatting issues.

test is implemented as a python script in test/python_modules/sequence/

test compares the calculation sequence to the calculation graph.

The test is run during compilation after parsing but before building.  By default, a failure will kill compilation, but
if IGNORE_SEQUENCE_ERRORS=1 in the environment, only a warning will be issued and compilation will continue.

Two out-of-order bugs are fixed.

1. Ordering simply counts how many inputs of a part of visited. When that number matches the total inputs for the part, the part is visited,
but inside a subystem, delays were counted twice.  Once on the initial pass looking for signal sources, and again as a normal part.

Parts that took input directly from delays could appear early in the sequence.

This change skips following links form delays as a normal part.

2. If a data source, including subsystem inputs, constants, delays, grounds were connected directly to a subsystem output, then
parts immediately connected from the output would be added to the subsystem sequence, though they were at a higher level.

This bug could cause these parts to be sequenced out of order.

Change is to check whether a part leading form a data source is in the subsystem.  This check is already included when following from normal (non-input) parts.

rtcds improvements

Closes #234, #276, #312, and #319

See merge request cds/advligorts!274

awgtpman: now fails gracefully when IOP is not running

Closes #246

See merge request cds/advligorts!273

uppercase characters in model names cause problems with the build system, so they are forbidden for most commands.

If models are already started when requested to start, there's no need to check. Systemd won't mind another request to start.
Removing these checks allows the user to specify a list of models to start, stop or restart, and not have to worry if some of them are already
in the requested state.

START_DELAY can be set to any value of seconds to change the default 15 second
delay after each model is started.  If the startup sequencer is used, the delay can be set to 1 second.

previously 'rtcds restart --all' would not restart the IOP model, since the kernel was unable to unload hte module before it was ordered to load it again.
Now, stopping a model waits until the kernel module is unloaded.

Also fails nicely if there's a version mismatch on the IOP mbuf.
Fixed mistake in logic that could allow tconv to run on IOP time when the IOP was not providing time.

RCG: some calculations were made out of order.

See merge request cds/advligorts!272

createDiagsFile.pm wass created as a refactoring of the feCodeGen.pl for writing the parts connections file.

Some global variables that were altered in this file were treated as locals, so the changes did not propagate
back to feCodeGen.pl.  This led to incorrect assessment that subsystems had no inputs, which meant subsystems could
be processed before their inputs, introducing a one cycle delay.

RCG: ADC read loop was only running once.

Closes #321

See merge request cds/advligorts!271

The loop was only running once for 65k IOP models with clock_div 2.  Not enough values were written to ADC, starving user models.

Less obviously, Fast ADC were not being decimated at the right rate.

Standard IOPs or slow ADCs on a fast IOP were unaffected, since the loop is meant to run once.

closes #321

RCG: virtualIOP=1 models do not compile.

See merge request cds/advligorts!270

This model adds necessary includes to virtualIOP models so that all needed symbols are available.

Disambiguate tag names in RCG

See merge request cds/advligorts!268

RCG: irigb skew generates an error when it's below 2 usec

See merge request cds/advligorts!267