Add a MODELRATE_CPS ( CPS ) variable to the model build.  Use this to calculate
dynamic limits for TIME0.

Change TIME0 measurement to always run on second cycle no matter the rate, and to
take rate into consideration for the calculation.

Fixes both fast (524K) and slow (33K) IOP models, specifically aimed at making LLO pemmid look good.

This model adds necessary includes to virtualIOP models so that all needed symbols are available.

LIGO PCIe timing card.  Otherwise, the lower limit remains unchanged.  But the displayed value only turns red below 2 no matter the timing, since MEDM is generated without knowledge of the timing system.

'IRIG-B' label on GDS-TP screen changed to 'TIME 0'

"TOTAL" time now reads this same IO time plus the time to run through all 'UNDERSAMPLE' or 'clock_div' model calculations.

For most models that amounts to only one calculation, but for a fast ADC model running at 524 Hz, but spitting out data at 65 Hz, that's all 8 calculations.

midstation configuration).Part of issue #231.

available with new PCIe timing card firmware.

Works with older PCIe card firmware, but now need to modify for latest
firmware (gpstime read as a single 64bit word).

now checks card count by type using new card_count array in
CDS_HARDWARE struct type. Still need to update user space code.

controllerxxx.c files.

same code as 1PPS sync.

of list to make virtual IOP models.

tests.

1) Moved sync21pps checking to sync21pps.c
2) Added WD signal to AI chassis diag for testing

error in AI chassis WD reporting on IO slot status.

1) Remove remnants of verify slot code, which was moved to moduleLoad.c previously.
2) Change to HKP_DAC_WD_CHK, now that DACs have common register map.
3) Some added/removed comments.

- IOP running on PCIe net time cannot have ligo timing card check in moduleLoad.c.
- For 1PPS testing, need to remove verify slots for controllerIop.c.

allows filling in the IOP_IO_STAT screen with useful info before kernel exit
when the IOP does not find the correct number of IO cards.

error message sent to GDSTP screen if PCIe cards do not line up
with IOC slots.

slot configuration tests.

using PCIe timing card. Error handling still required. Sync21PPS should
now work with any type ADC card in first slot.

change is define of a common DAC register structure in gsc_dac_common.h.
This replaces the former 3 separate defs, one for each DAC type.

isn't ready yet.  Backing it out.

in prep for card2slot mapping verification code.