general duotone improvements
Daniel writes:
One more item to add:
We should give the DAC duotone readbacks the same treatment as the ADC, and either repurpose the DT_TIME_DAC channel as a float or add another float channel.
The analysis windows also needs to be shifted. Looks like we have a delay of 4 samples at 64K? If so, we may want to subtract it in the reporting.
Only 2 FE are using DAC duotone as far as I know.
He also wrote
Here is my list of high priority features for the next RCG release. Not sure if these changes will fit before it gets released. In any case, these should be implemented in the OMC FE as soon as possible.
DuoTone calculation in 512K IOP/ADC uses 5th sample (the one that is aligned to 1PPS) for the zero crossing calculation. This guarantees that DT zero crossings are reported consistently between all IOPs, and represent the true delay or advance of the DAQ timestamps.
DuoTone zero crossing limits that take into account newer timing board firmware with corrected DT signal, i.e., DT signal crosses zero at 1PPS sharp.
Fix the extra 13.4 us IPC delay in the 512K IOP. I assume this is because an 512K IOP writes its IPCs after the first rather than the last sample.
Make an option to start the user models after the IOP has finished with is FE model and written all IPC, in order to eliminate the IOP IPC delays all together. Probably needs a lot of testing to see if the timing works out. (Also, IPCs would need to be written without the 1 IOP cycle advance as it currently is done.)
Here is the> effect testing data windows of
zeroCrossing[dat, 5, 11], zeroCrossing[dat, 5, 12], zeroCrossing[dat, 5, 13], zeroCrossing[dat, 6, 12], zeroCrossing[dat, 4, 9], zeroCrossing[dat, 6, 13]
and compare it to a full fit (blue current algorithm, red new, units usec).
Here is a histogram of all duotone zero crossings: There seems to be 2 separate distributions spaced 600ns apart. Strange. Not sure, if this is a timing board thing or not.
Next Tuesday, we should reprogram 1 to 3 timing boards with the new firmware, omc and isc ex/ey maybe. I think we should not replace the boards but reprogram them to make sure they jump exactly the specified difference of 7.1us.
We can also downgrade the firmware for the one in the test stand.