Duotone loopback test suggests unaccounted for delay in DAC transmit.
Overview
While verifying DAC output data was not shifted in time after a timing glitch recovery, two observations have been made that need explanation.
- The calculated delay on a AI/AA chassis loopback duotone DAC signal, is around
164.5 us
- This is much higher than the expected
~45.78 us
3 cycle delay - We need to determine were the additional delay is coming from
- Additional testing showed that more delay than expected was coming from the model, however the AI and AA chassis are still causing unexpected delays.
- optimizeIO/Using FIFO decreased the measured delay from
177 us
to130 us
on the with 16 Bit ADCs. - When the AI/AA was replaced with the loopback chassis, the 1
77 us
delay decreased to99 us
- optimizeIO/Using FIFO decreased the measured delay from
- This is much higher than the expected
- The variation in the measured delay between channels and DAC cards is on the order of
0.28 - 1.6 us
- This appears to be too high if DACs are all sharing the same clock.
Model setup
Measurement Methods
The ADC inputs are collected with the DAQ and queried on a one second boundary. Code from here is adapted to do the offset calculation. Calculation correctly calculates ~7.36 us offset on initial duotone signal.
Single Measurement
Going to request time at 1372197165
Chan: X2:IOP-SUS_H56_MADC0_TP_CH31_DQ, delay (us): 7.359629239027071
Chan: X2:SUS-DUO_TP_DQ, delay (us): 7.359629239027071
Chan: X2:SUS-ADC0_C0_TP_DQ, delay (us): 164.61115178793298
Chan: X2:SUS-ADC0_C1_TP_DQ, delay (us): 164.9197192128856
Chan: X2:SUS-ADC0_C2_TP_DQ, delay (us): 165.28886281619992
Chan: X2:SUS-ADC0_C3_TP_DQ, delay (us): 164.89359785275113
Chan: X2:SUS-ADC0_C8_TP_DQ, delay (us): 164.51672872566462
Chan: X2:SUS-ADC0_C9_TP_DQ, delay (us): 163.9457030241185
Chan: X2:SUS-ADC0_C10_TP_DQ, delay (us): 164.8939940880844
Chan: X2:SUS-ADC0_C11_TP_DQ, delay (us): 164.67402830800225
Chan: X2:SUS-ADC0_C16_TP_DQ, delay (us): 165.39130934072787
Chan: X2:SUS-ADC0_C17_TP_DQ, delay (us): 165.23138935851782
Chan: X2:SUS-ADC0_C18_TP_DQ, delay (us): 166.21500563539774
Chan: X2:SUS-ADC0_C19_TP_DQ, delay (us): 166.17057905318777
Chan: X2:SUS-ADC0_C24_TP_DQ, delay (us): 166.0766935048718
Chan: X2:SUS-ADC0_C25_TP_DQ, delay (us): 165.64117533518848
Chan: X2:SUS-ADC0_C26_TP_DQ, delay (us): 165.47702618695703
Chan: X2:SUS-ADC0_C27_TP_DQ, delay (us): 165.65296226260858
All 18bit DACs (Original Config) (AI and AA Chassis)
Line color signals what DAC the channel is being looped through.
All 16 Bit DACs (AI and AA Chassis)
Line color signals what DAC the channel is being looped through.
All 16 Bit DACs - Loopback Chassis
Line color signals what DAC the channel is being looped through.
Channel to channel max difference of ~31 ns, a reasonable value.
Edited by Ezekiel Dohmen