Skip to content
Snippets Groups Projects
Commit dc4fb84b authored by Patrick Godwin's avatar Patrick Godwin
Browse files

gstlal_idq_trigger_gen: corrected latency in firbank to be in num samples, not time

parent 8970b045
No related branches found
No related tags found
No related merge requests found
......@@ -350,7 +350,7 @@ for channel in channels:
phase = [0, numpy.pi/2.]
durations[(channel, rate)] = dur
thishead = pipeparts.mkqueue(pipeline, thishead, max_size_buffers = 0, max_size_bytes = 0, max_size_time = Gst.SECOND * 30)
thishead = pipeparts.mkfirbank(pipeline, thishead, fir_matrix = numpy.array([sine_gaussian(phi, phi_0, q, t_arr) for (phi, q) in phi_ql(flow, fhigh, qlow, qhigh) for phi_0 in phase]), time_domain = False, block_stride = int(rate), latency = dur/2)
thishead = pipeparts.mkfirbank(pipeline, thishead, fir_matrix = numpy.array([sine_gaussian(phi, phi_0, q, t_arr) for (phi, q) in phi_ql(flow, fhigh, qlow, qhigh) for phi_0 in phase]), time_domain = False, block_stride = int(rate), latency = int(rate*dur/2))
thishead = pipeparts.mkqueue(pipeline, thishead, max_size_buffers = 1)
thishead = pipeparts.mktogglecomplex(pipeline, thishead)
thishead = pipeparts.mkcapsfilter(pipeline, thishead, caps = "audio/x-raw, format=Z64LE, rate=%i" % rate)
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment