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Commit da051f47 authored by Rolf Bork's avatar Rolf Bork
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Start of adding support for multiple IOC with new timing cards (Issue #231). 

Works with older PCIe card firmware, but now need to modify for latest
firmware (gpstime read as a single 64bit word).
parent b98d117b
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src/fe/controllerIop.c
+ 2
− 2
View file @ da051f47
......@@ -328,7 +328,7 @@ fe_start_controller( void* arg )
if ( cdsPciModules.card_count[ CON_1616DIO ] )
syncSource = SYNC_SRC_TDS;
// If PCIe timing card found (IOC Gen2), use that for startup sync
else if ( cdsPciModules.ligo_timing_card )
else if ( cdsPciModules.card_count[ LPTC ] > 0 )
syncSource = SYNC_SRC_LTC;
// If not on aligo timing system, will try to sync to 1PPS signal on ADC
// This is legacy support for non-LIGO sites that still use an eLIGO
......@@ -382,7 +382,7 @@ fe_start_controller( void* arg )
// If test system has LIGO PCIe timing card, then start clocks
case SYNC_SRC_LTC:
// Set status to slot checking
pLocalEpics->epicsOutput.fe_status = IOC_SLOT_CHK;
// pLocalEpics->epicsOutput.fe_status = IOC_SLOT_CHK;
// Card map to bp slot verification
lptc_enable_all_slots( &cdsPciModules );
lptc_start_clock( &cdsPciModules );
......
src/fe/moduleLoad.c
+ 1
− 1
View file @ da051f47
......@@ -136,7 +136,7 @@ rt_fe_init( void )
// If IOP and LIGO PCIe timing card present,
// verify that PCIe cards line up with proper
// backplane slot.
if ( cdsPciModules.ligo_timing_card )
if ( cdsPciModules.card_count[ LPTC ] == 1 )
{
// Set status to slot checking
pLocalEpics->epicsOutput.fe_status = IOC_SLOT_CHK;
......
src/include/drv/cdsHardware.h
+ 2
− 2
View file @ da051f47
......@@ -28,6 +28,7 @@
/* Define maximum number of each PCI module supported. */
#define MAX_IOC 2
#define MAX_ADC_MODULES 12
#define MAX_ADC_CHN_PER_MOD 32
#define MAX_DAC_MODULES 12
......@@ -235,8 +236,7 @@ typedef struct CDS_HARDWARE{
int dolphinCount; /* the number of Dolphin cards we have on the system */
volatile unsigned long *dolphinRead[4]; /* read and write Dolphin memory */
volatile unsigned long *dolphinWrite[4]; /* read and write Dolphin memory */
int ligo_timing_card; /* the number of Dolphin cards we have on the system */
volatile unsigned int *lptc; /* LIGO PCIe Timing card */
volatile unsigned int *lptc[MAX_IOC]; /* LIGO PCIe Timing card */
unsigned int ioc_config[MAX_ADC_MODULES];
unsigned int ioc_instance[MAX_ADC_MODULES];
unsigned int ioc_cards;
......
src/include/drv/ligoPcieTiming.c
+ 121
− 77
View file @ da051f47
......@@ -14,20 +14,36 @@ lptcInit( CDS_HARDWARE* pCds, struct pci_dev* lptcdev )
unsigned int tsec;
unsigned int regval;
int ii;
int card = 0;
u64 gpstime;
card = pCds->card_count[ LPTC ];
status = pci_enable_device( lptcdev );
printk( "Xilinx enabled status = %d\n", status );
pci_read_config_dword( lptcdev, PCI_BASE_ADDRESS_0, &pci_io_addr );
pci_io_addr &= 0xfffffff0;
addr = (char*)ioremap_nocache( (unsigned long)pci_io_addr, 0x2000 );
printk( "Xilinx mapped = 0x%x 0x%p\n", pci_io_addr, addr );
pCds->lptc = (unsigned int*)addr;
pCds->ligo_timing_card = 1;
pCds->lptc[ card ] = (unsigned int*)addr;
pCds->gps = (unsigned int*)addr;
pCds->gpsType = LIGO_RCVR;
if ( card == 0 )
{
pCds->gps = (unsigned int*)addr;
pCds->gpsType = LIGO_RCVR;
}
lptcPtr = (LPTC_REGISTER*)addr;
lptcPtr2 = (LPTC_REGISTER_2*)addr;
gpstime = lptcPtr2->gps_time;
usec = gpstime & 0xffffffff;
sec = (gpstime >> 32) & 0xffffffff;
printk( "Xilinx test = %u %u\n", sec, usec );
udelay(1000);
gpstime = lptcPtr2->gps_time;
usec = gpstime & 0xffffffff;
sec = (gpstime >> 32) & 0xffffffff;
printk( "Xilinx test = %u %u\n", sec, usec );
sec = lptcPtr->gps_sec;
usec = lptcPtr->gps_nano * LPTC_USEC_CONVERT;
......@@ -59,54 +75,56 @@ lptcInit( CDS_HARDWARE* pCds, struct pci_dev* lptcdev )
printk( "LPTC backplane present = OK\n" );
else
printk( "LPTC IS NOT PRESENT \n" );
pCds->card_count[ LPTC ]++;
}
void
lptc_enable_all_slots( CDS_HARDWARE* pCds )
{
unsigned int regval;
int ii;
unsigned int regval;
int ii, jj;
LPTC_REGISTER* lptcPtr;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
switch ( pCds->ioc_config[ ii ] )
lptcPtr = (LPTC_REGISTER*)pCds->lptc[ jj ];
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
{
case GSC_18AI64SSC:
case GSC_18AI32SSC1M:
switch ( pCds->ioc_config[ ii ] )
{
case GSC_18AI64SSC:
case GSC_18AI32SSC1M:
#ifdef SERVO512K
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_FAST );
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_FAST );
#else
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_SLOW );
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_SLOW );
#endif
break;
case GSC_16AI64SSA:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_SLOW );
break;
case GSC_16AO16:
case GSC_18AO8:
case GSC_20AO8:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_DAC_SET | IOC_CLK_SLOW );
break;
default:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_FAST );
break;
break;
case GSC_16AI64SSA:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_SLOW );
break;
case GSC_16AO16:
case GSC_18AO8:
case GSC_20AO8:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_DAC_SET | IOC_CLK_SLOW );
break;
default:
lptcPtr->slot_info[ ii ].config =
( LPTC_SCR_ADC_SET | IOC_CLK_SLOW );
break;
}
if ( ii == 0 )
lptcPtr->slot_info[ ii ].config |= LPTC_SCR_ADC_DT_ENABLE;
udelay( MAX_UDELAY );
regval = lptcPtr->slot_info[ ii ].config;
}
if ( ii == 0 )
lptcPtr->slot_info[ ii ].config |= LPTC_SCR_ADC_DT_ENABLE;
udelay( MAX_UDELAY );
regval = lptcPtr->slot_info[ ii ].config;
}
udelay( MAX_UDELAY );
udelay( MAX_UDELAY );
}
int
......@@ -114,7 +132,7 @@ lptc_get_gps_time( CDS_HARDWARE* pCds, unsigned int* sec, unsigned int* nsec )
{
unsigned int regval;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
*sec = lptcPtr->gps_sec;
regval = lptcPtr->gps_nano;
*nsec = regval * LPTC_USEC_CONVERT;
......@@ -126,7 +144,7 @@ lptc_get_gps_nsec( CDS_HARDWARE* pCds )
unsigned int regval;
unsigned int timeval;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
regval = lptcPtr->gps_nano;
timeval = regval * LPTC_USEC_CONVERT;
return timeval;
......@@ -136,7 +154,7 @@ lptc_get_gps_sec( CDS_HARDWARE* pCds )
{
unsigned int regval;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
regval = lptcPtr->gps_sec;
return regval;
}
......@@ -144,37 +162,41 @@ lptc_get_gps_sec( CDS_HARDWARE* pCds )
int
lptc_get_slot_config( CDS_HARDWARE* pCds, int slot )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
return ( lptcPtr->slot_info[ slot ].config & 0xffffff );
}
int
lptc_get_slot_status( CDS_HARDWARE* pCds, int slot )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
return ( lptcPtr->slot_info[ slot ].status & 0xffffff );
}
int
lptc_start_clock( CDS_HARDWARE* pCds )
{
int ii;
int ii, jj;
LPTC_REGISTER* lptcPtr;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
lptcPtr->bp_config = LPTC_CMD_START_CLK_ALL;
// Update lptc status to epics
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
pLocalEpics->epicsOutput.lptMon[ ii ] =
lptc_get_slot_status( &cdsPciModules, ii );
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
pLocalEpics->epicsOutput.lptMon[ ( ii + LPTC_IOC_SLOTS ) ] =
lptc_get_slot_config( &cdsPciModules, ii );
pLocalEpics->epicsOutput.lpt_bp_config =
lptc_get_bp_config( &cdsPciModules );
pLocalEpics->epicsOutput.lpt_bp_status =
lptc_get_bp_status( &cdsPciModules );
pLocalEpics->epicsOutput.lpt_status =
lptc_get_lptc_status( &cdsPciModules );
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
lptcPtr = (LPTC_REGISTER*)pCds->lptc[ jj ];
lptcPtr->bp_config = LPTC_CMD_START_CLK_ALL;
// Update lptc status to epics
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
pLocalEpics->epicsOutput.lptMon[ ii ] =
lptc_get_slot_status( &cdsPciModules, ii );
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
pLocalEpics->epicsOutput.lptMon[ ( ii + LPTC_IOC_SLOTS ) ] =
lptc_get_slot_config( &cdsPciModules, ii );
pLocalEpics->epicsOutput.lpt_bp_config =
lptc_get_bp_config( &cdsPciModules );
pLocalEpics->epicsOutput.lpt_bp_status =
lptc_get_bp_status( &cdsPciModules );
pLocalEpics->epicsOutput.lpt_status =
lptc_get_lptc_status( &cdsPciModules );
}
return lptcPtr->bp_status;
}
......@@ -184,7 +206,7 @@ lptc_status_update( CDS_HARDWARE* pCds )
{
int ii;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
// Update lptc status to epics
for ( ii = 0; ii < LPTC_IOC_SLOTS; ii++ )
pLocalEpics->epicsOutput.lptMon[ ii ] =
......@@ -198,44 +220,49 @@ lptc_status_update( CDS_HARDWARE* pCds )
lptc_get_bp_status( &cdsPciModules );
pLocalEpics->epicsOutput.lpt_status =
lptc_get_lptc_status( &cdsPciModules );
}
int
lptc_stop_clock( CDS_HARDWARE* pCds )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
lptcPtr->bp_config = LPTC_CMD_STOP_CLK_ALL;
udelay( MAX_UDELAY );
udelay( MAX_UDELAY );
int jj;
LPTC_REGISTER* lptcPtr;
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
lptcPtr = (LPTC_REGISTER*)pCds->lptc[ jj ];
lptcPtr->bp_config = LPTC_CMD_STOP_CLK_ALL;
udelay( MAX_UDELAY );
udelay( MAX_UDELAY );
}
return lptcPtr->bp_status;
}
int
lptc_get_lptc_status( CDS_HARDWARE* pCds )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
return lptcPtr->status;
}
int
lptc_get_bp_status( CDS_HARDWARE* pCds )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
return lptcPtr->bp_status;
}
int
lptc_get_bp_config( CDS_HARDWARE* pCds )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
return lptcPtr->bp_config;
}
void
lptc_dac_duotone( CDS_HARDWARE* pCds, int setting )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
if ( setting )
{
lptcPtr->slot_info[ 0 ].config |= LPTC_SCR_DAC_DT_ENABLE;
......@@ -251,25 +278,42 @@ lptc_dac_duotone( CDS_HARDWARE* pCds, int setting )
void
lptc_slot_clk_set( CDS_HARDWARE* pCds, int slot, int enable )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
if ( enable ) lptcPtr->slot_info[ slot ].config |= LPTC_SCR_CLK_ENABLE;
else lptcPtr->slot_info[ slot ].config &= ~( LPTC_SCR_CLK_ENABLE );
int jj;
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ 0 ];
if ( enable )
lptcPtr->slot_info[ slot ].config |= LPTC_SCR_CLK_ENABLE;
else
lptcPtr->slot_info[ slot ].config &= ~( LPTC_SCR_CLK_ENABLE );
}
}
void
lptc_slot_clk_disable_all( CDS_HARDWARE* pCds )
{
int slot = 0;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
for (slot=0; slot< LPTC_IOC_SLOTS; slot ++)
lptcPtr->slot_info[ slot ].config &= ~( LPTC_SCR_CLK_ENABLE );
int jj;
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ jj ];
for ( slot = 0; slot < LPTC_IOC_SLOTS; slot++ )
lptcPtr->slot_info[ slot ].config &= ~( LPTC_SCR_CLK_ENABLE );
}
}
void
lptc_slot_clk_enable_all( CDS_HARDWARE* pCds )
{
int slot = 0;
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc;
for (slot=0; slot< LPTC_IOC_SLOTS; slot ++)
lptcPtr->slot_info[ slot ].config |= LPTC_SCR_CLK_ENABLE;
int jj;
for ( jj = 0; jj < pCds->card_count[ LPTC ]; jj++ )
{
LPTC_REGISTER* lptcPtr = (LPTC_REGISTER*)pCds->lptc[ jj ];
for ( slot = 0; slot < LPTC_IOC_SLOTS; slot++ )
lptcPtr->slot_info[ slot ].config |= LPTC_SCR_CLK_ENABLE;
}
}
src/include/drv/ligoPcieTiming.h
+ 10
− 0
View file @ da051f47
......@@ -40,6 +40,16 @@ typedef struct LPTC_REGISTER {
u32 reserved3; // 0x001c
SLOT_CONFIG slot_info[10]; // 0x0020
}LPTC_REGISTER;
typedef struct LPTC_REGISTER_2 {
u64 gps_time; // 0x0000
u32 status; // 0x0008
u32 revision; // 0x000c
u32 bp_config; // 0x0010
u32 wd_reset; // 0x0014
u32 bp_status; // 0x0018
u32 reserved3; // 0x001c
SLOT_CONFIG slot_info[10]; // 0x0020
}LPTC_REGISTER_2;
typedef struct LPTC_OBF_REGISTER {
u32 brd_config; // 0x0180
......
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