of cpu clock time, if available.

data from IOP via shared memory.

1) feCodeGen and Parameter.pm: Added necessary settings for rates
   up to 512K sampling rate.
2) Parameter.pm now sets the SERVO rate compile flag eg -DSERVO64K
3) Added support for fast ADC GSC18AI64, for user app models in
   mapApp.c.
4) Changes in iop_adc_read() for mixed clock ADCs support.

1) For now, the RCG will accept either ifo= or site=, eg ifo=X2 or site=X2 to designate the IFO in the cdsParameter block. This
    obviates the need for immediate changes to present Matlab control models. All new models, and eventually all old models,
    should use the ifo= designator as the site= designator will be deprecated in a TBD future release.
2) At compile time, if a model still contains the site= designator, a warning message will be written to alert user to change to ifo=.
     This is simply a warning for now.
3) I have gone thru all the RCG Perl code to change site to ifo, where appropriate.  I think things are consistent now ie site is a
     location eg lho, llo, lao, etc. and ifo is the IFO designator eg ifo=H1, L1, A1, etc.

- Added check in ADC initialization code.
- Passed back as a new ADC status bit (3)
- Added status bit to GDS_TP screen ADC status
- Since difficult to remember what bits mean, ADC status bit info
  added with labels to the auto generated MONITOR_ADC screens.
- Note that this bit is only reported by IOP models.

provides a listing of available Parameter block settings.

IOP: setting virtualiop=1 will force all IPCs defined in the model to
	become SHMEM type regardless of model definintion.
USER APP: setting use_shm_ipc=1 will force all IPCs defined in the model to
        become SHMEM type regardless of model definintion.
See README file in advligorts/src/fe directory for fulldetails of
Parameter block options.

   - Deprecated old, non-functional on Debian 10, controllerVirtual.c.
   - Parameter block entry "virtualIOP=1" sets the appropriate compile flags.
   - controllerIOP.c modified with addition of RUN_WO_IO_MODULES option
   - Added timing control in time_slave_io.c
Further changes are still required to feed data into the ADC inputs.  As is,
ADC inputs are statically set to value of channel number eg channel 31= 31.

  - Moved send_io_info_to_mbuf routine from map.c to moduleLoadCommon.c, as the
    TIME_SLAVE option does not use map.c.
  - Changed controllerIop.c to not write DAC bit registers if TIME_SLAVE, as
    this area is not mapped for this configuration ie no I/O modules.

  - Set all IPC between computers to use Dolphin ie deprecated support for GeFanuc RFM.
	- This removes the need for the USE_LR_PCIE file in src/include to trigger compile option.
  - Set the default to use Dolphin Gen 2 (IX) drivers
	- This removes the need for the USE_DOLPHIN_GEN2 file in src/include to trigger compile option.
	- Added Parameter block entry option dolphingen=1

code files (controlerLR.c) to handle cases where an FE is connected via a long rnage fiber
to its I/O chassis.  The specific LIGO case is PEM midstations and future A+
systems. The generic controllerIOP.c now handles this case via Parameter block settings.
See the README file in src/fe directory for description of those settings.
This change also allowed for the removal of special case subroutines in the src/include/drv
area C code files.

Change to timing.c to use ligo_get_gps_offset in calc current time.

Got rid of no longer used files.
Added a README that lists code needed for each build configuration of FE code.

	- Added delay to kernel object startup in moduleLoad
		- Used to be done in RCG startup script
	- Added check for correct number of PCIe cards found
		- Code now exits if REQUIRE_IO_CNT compile flag is set
		  (require_io_cnt = 1 in model Parameter block)
		- Error message sent to EPICS fe_status
	- Moved mbuf attachments out of moduleLoadIop and moduleLoadApp into
	  moduleLoadCommon.c, since common to both.

	- Fix for channel hopping detection
	- Update to moduleLoadCommon printk to dmesg for module info.

Note: Error messages will not be sent to dmesg until fe code is unloaded
using either kill<model_name> or rmmod <model_name> command.

initialization fails.

This is a first cut ie not ready for final merge.

during fast ADC testing.

TDS timing available.

  - Prematurely ran clang, so unfortunately looks like lots of diffs.
  - Added module initialization for card model numbers being passed to user apps.
    - Without this, user model could mistake a zero as an ADC if IOP does not have the
      right number of cards, such as in a test stand.
  - Added 2msec delay before starting core locked thread to allow time for printk
    buffers to be flushed.

Simply ran clang-format on new mapVirtual.c and time_slave_io.c files that support time slave via Dolphin.

This change also include Keith's changes for latest Dolphin driver code.